Low latency soft decoder architecture for generalized product codes

ABSTRACT

Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, a system accesses and decodes a generalized product code (GPC) codeword by using at least one of a plurality of Chase decoding procedures available on the system. A first Chase decoding procedure is configured according to first values for a set of decoding parameters. A second Chase decoding procedure is configured according to second values for the set of decoding parameters. The second values are different from the first values. The first Chase decoding procedure has a smaller latency and a higher bit error rate (BER) relative to the second Chase decoding procedure based on the first values and the second values for the set of decoding parameters.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional ApplicationNo. 62/373,935, entitled “Low Latency Soft Decoder Architecture forGeneralized Product Codes,” filed Aug. 11, 2016, commonly owned andexpressly incorporated by reference herein in its entirety.

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BACKGROUND

In NAND flash storage, the most widely used advanced error controlcoding techniques are based on low density parity check (LDPC) codes andBose-Chaudhuri-Hocquenghem (BCH) codes. Although BCH codes have hardwarefriendly implementation, they can be unattractive due to lack of softdecoding support when several NAND reads are used to generate the softinformation. LDPC soft decoder provides significant performance gains.However, the LDPC decoder has a large System on a Chip (SoC) area andconsumes relatively more power.

Given the shortcomings of LDPC and BCH codes, a class of codes has beendeveloped, where these codes can support soft decision decoding with asmaller SoC area and smaller power consumption. These codes includeproduct codes. U.S. Pat. No. 9,231,623, entitled “Chase Decoding forTurbo-Product Codes (TPC) Using Error Intersections,” filed Mar. 26,2014, U.S. patent application Ser. No. 15/158,425, entitled “GeneralizedProduct Codes For NAND Flash Storage,” filed May 18, 2016, and U.S.patent application Ser. No. 15/460,155, filed Mar. 15, 2017, entitled“Soft Decoder for Generalized Product Codes,” all of which are commonlyassigned and expressly incorporated by reference herein in theirentirety, describe examples of such codes and decoding thereof.

Product codes can provide significant performance gains in hard decisiondecoding with much lesser SoC area and power compared to LDPC codes. InU.S. patent application Ser. No. 15/460,155, filed Mar. 15, 2017,entitled “Soft Decoder for Generalized Product Codes,” a soft decoderarchitecture is described. This architecture provides soft decodingperformance close to LDPC codes. In addition to SoC area and powerbenefits, Product codes are competitive in throughput compared to LDPCcodes.

However, latency of the soft decoder of generalized product codes (GPC)can be quite high compared to the LDPC soft decoder. In U.S. patentapplication Ser. No. 15/158,416, entitled “Performance Optimization InSoft Decoding For Turbo Product Codes,” filed May 18, 2016, which iscommonly assigned and expressly incorporated by reference herein in itsentirety, an early termination algorithm for Chase decoding isdescribed. The early termination algorithm can reduce latency of thesoft decoder. Although this latency reduction is significant, the LDPCdecoder remains a faster soft decoder.

Many product applications can be latency sensitive with respect to hardand/or soft decision decoding. For example, and in order to make the GPCsolution viable for mobile, client and enterprise applications,significant reduction in soft decoder latency is further needed.

BRIEF SUMMARY

Techniques for codeword decoding are described. The techniques can beimplemented within a system and reduce the overall decoding latency ofthe system without a significant impact to the bit error rate (BER)performance. In an example, the multiple Chase decoding procedures areavailable on the system. For example, each Chase decoding procedure isimplemented by a soft decoder of the system. Generally, the Chasedecoding procedures use the same decoding algorithm to decode GPCcodewords. Accordingly, the Chase decoding procedures share a common setof decoding parameters. However, the values of the decoding parametersvary across the different Chase decoding procedures. In particular, thevalues are set for each Chase decoding procedure to achieve a particulardecoding latency for that procedure. For instance, first values may beused for a first Chase decoding procedure and second, different valuesmay be used for a second Chase decoding procedure. Based on thesevalues, the first Chase decoding procedure can have a better decodinglatency (e.g., a smaller one), but a worse BER (e.g., a higher one)relative to the second Chase decoding procedure. The system uses atleast one of the Chase decoding procedures to decode GPC codewords.

In an example, the soft decoders are connected in series. The firstChase decoding procedure in the series can have the fastest decodinglatency, but the worst BER. In comparison, the last Chase decodingprocedure in the series can have the slowest decoding latency, but thebest BER. A GPC codeword is input to the first soft decoder. Only if adecoding failure occurs at that decoder, the GPC codeword becomes inputto the next soft decoder in the series, and so on and so forth.

In an example, the soft decoders are provided in parallel. Informationabout the BER is available at the time of decoding. A mapping is alsoavailable, where the mapping associates the soft decoders with BERranges. A comparison of the BER to the BER ranges is made and one of thesoft decoder is selected. A GPC codeword is input to the selected softdecoder for decoding.

BRIEF DESCRIPTION OF THE DRAWINGS

An understanding of the nature and advantages of various embodiments maybe realized by reference to the following figures. In the appendedfigures, similar components or features may have the same referencelabel. Further, various components of the same type may be distinguishedby following the reference label by a dash and a second label thatdistinguishes among the similar components. If only the first referencelabel is used in the specification, the description is applicable to anyone of the similar components having the same first reference labelirrespective of the second reference label.

FIG. 1 illustrates an example high level block diagram of an errorcorrecting system, in accordance with certain embodiments of the presentdisclosure.

FIG. 2A and FIG. 2B are simplified schematic diagrams illustrating ageneralized product code (GPC), in accordance with certain embodimentsof the present disclosure.

FIG. 3 illustrates an example configuration of a decoder that implementsmultiple Chase decoding procedures, in accordance with certainembodiments of the present disclosure.

FIG. 4 illustrates another example configuration of a decoder thatimplements multiple Chase decoding procedures, in accordance withcertain embodiments of the present disclosure.

FIG. 5 illustrates an example flow for decoding a codeword based on atleast one of a plurality of decoders available on a system, inaccordance with certain embodiments of the present disclosure.

FIG. 6 illustrates an example flow for decoding a codeword based on aseries of decoders, in accordance with certain embodiments of thepresent disclosure.

FIG. 7 illustrates an example flow for decoding a codeword based onparallel decoders, in accordance with certain embodiments of the presentdisclosure.

FIG. 8 illustrates an example flow for configuring the system to achievea desired decoding performance, where the system provides a plurality ofdecoders, in accordance with certain embodiments of the presentdisclosure.

FIG. 9 describes one potential implementation of a system, which may beused according to one embodiment.

DETAILED DESCRIPTION

A detailed description of one or more embodiments of the invention isprovided below along with accompanying figures that illustrate theprinciples of the invention. The invention is described in connectionwith such embodiments, but the invention is not limited to anyembodiment. The scope of the invention is limited only by the claims andthe invention encompasses numerous alternatives, modifications, andequivalents. Numerous specific details are set forth in the followingdescription in order to provide a thorough understanding of theinvention. These details are provided for the purpose of example and theinvention may be practiced according to the claims without some or allof these specific details. For the purpose of clarity, technicalmaterial that is known in the technical fields related to the inventionhas not been described in detail so that the invention is notunnecessarily obscured.

Embodiments of the present disclosure relate to a novel soft decoderarchitecture that reduces the latency in a desired decoding regime forlatency-sensitive product applications. In an example embodiment, asystem uses Chase decoding to decode GPC codewords. Multiple Chasedecoding procedures are available on the system. Each Chase decodingprocedure is configured according to particular values for a set ofdecoding parameters. This set is common across the Chase decodingprocedures. For example, the set includes a first parameter “L” andsecond parameter “S,” in which case Chase decoding can be referred to asChase (L,S) decoding. The first parameter “L” limits the total number ofbits of a GPC codeword available for flipping across multiple flips tocorrect errors in the decoded codeword. The second parameter “S” limitsthe total number of the bits available for flipping in a single flip.For instance, in a Chase (4,2) decoding procedure, four bits of a GPCcodeword can be flipped, where each time the bits are flipped, acombination of two bits to be flipped should be used. By varying thevalues of the decoding parameters, each decoding procedure can beoptimized for either latency or bit error rate (BER). For example, thesmaller the first parameter “L” is, the faster the Chase decodingprocedure is (e.g., the smaller its decoding latency is), but the worseits BER is (e.g., the larger the BER is). The system intelligently usesat least one of the Chase decoding procedures to decode a GPC codeword.For instance, the fastest Chase decoding procedure is used (e.g., theones with the smallest decoding latency). If the resulting BER isacceptable, no additional decoding is needed. Otherwise, anotherdecoding procedure is used. Accordingly, the overall decoding latency ofthe system is reduced given the intelligent use of the Chase decodingprocedures.

To illustrate, the available Chase decoding procedures include a firstChase decoding procedure and a second Chase decoding procedure. Thefirst Chase decoding procedure is configured according to first valuesof the decoding parameters (e.g., “L” set to six and “S” set to one). Asecond Chase decoding procedure is configured according to second valuesof the decoding parameters (e.g., “L” set to twelve and “S” set tofive). In this example, the first Chase decoding procedure is faster(e.g., has a relatively smaller latency), but has a worse BERperformance (e.g., has a relatively larger BER) than the second onegiven the values used for the common set of decoding parameters “L” and“S.” The system can use the first decoding procedure to decode GPCcodewords if the first BER performance is acceptable.

Different techniques are possible to use the available Chase decodingprocedures. In one example technique, these procedures are connected inseries. The first Chase decoding procedure in the series is generallythe fastest, but has the worse BER. Conversely, the last chase decodingprocedure in the series is the slowest, but has the best BER. A GPCcodeword is input to one of the Chase decoding procedures (e.g., to thefirst one). If its decoding fails, the GPC codeword is then input to thenext connected Chase decoding procedure (e.g., to the second one in theseries), and so on and so forth. If the decoding succeeds, the GPCcodeword need no longer be an input to the next connected Chase decodingprocedure.

In another example technique, the available Chase decoding proceduresare set-up in parallel. A mapping is also available on the system (e.g.,from memory). This mapping specifies a selection of a particular Chasedecoding procedure given a BER range. Accordingly, the system uses a BERestimate and the mapping to select one of the Chase decoding procedure.For instance, the selected procedure has a BER range to which the BERestimate belongs. Thereafter, the system decodes GPC codewords by usingthe selected Chase decoding procedure.

In the interest of clarity of explanation, the embodiments of thepresent disclosure are described in connection with GPC codewords andChase decoding procedures. However, the embodiments are not limited assuch and similarly apply to other types of codes, such as turbo producecodes (TPC) and Generalized LDPC (G-LDPC codes), and other types of hardand/or soft decoding procedures. Generally, multiple decoding procedureare available on the system in, for example, series or parallel. Thesedecoding procedure implement a same decoding algorithm and areconfigured according to a common set of decoding parameters for theexecution of the decoding algorithm. The values of the decodingparameters are varied across the decoding procedures to vary theperformances. For instance, one set of values for a first decodingprocedure is set to optimize latency (e.g., reduce the latency), but canresult in a high BER. The values of a second decoding procedure is setto optimize the BER (e.g., reduce the BER), but can result in a highlatency. These two decoding procedures can be used in conjunction(whether in series or in parallel) to achieve an overall decodinglatency and BER.

The term “error correcting code (ECC)” is used herein to refer to acodeword that is generated by a process of adding redundant data, orparity data, to a message, such that it can be recovered by a receivereven when a number of errors are introduced, either during the processof transmission, or storage. In general, ECC decoding can correct one ormore errors up to the capability of the code being used.Error-correcting codes are frequently used in communications, as well asfor reliable storage in storage systems such as CDs, DVDs, hard disks,and random access memories (RAMs), flash memories, and the like. Errorcorrecting codes include GPC codes.

The term “hard decision” is used herein to refer to a bit that comprisesa “0” or a “1” value, and is associated with a particular locationwithin a codeword. A “hard decision” may also be referred to as a “hardoutput” or “hard information.” In some embodiments, the reliability ofeach hard decision may be known. The “reliability” of a hard decisionrefers to a probability (e.g., a value from “0” through “1”) that thecorresponding hard decision is correct. A “reliability” may also bereferred to as “soft information” or a “soft output.” In a NAND channel,a reliability for each bit may be obtained, for example, by multipleread operations from the NAND memory using different thresholds. Ingeneral, if the hard decision decoding of a codeword fails, softinformation can be used to decode the failed codeword using softdecoding techniques, such as Chase decoding.

FIG. 1 illustrates an example high level block diagram of an errorcorrecting system 100, in accordance with certain embodiments of thepresent disclosure. In the example shown, the system includes 100 anencoder 110, a storage system 120, a detector 130, and a decoder 140.The encoder 110 receives information bits that include data which isdesired to be stored in the storage system 120 or transmitted in acommunications channel. Encoded data is output by the encoder 110 and iswritten to the storage system 120. In various embodiments, the storagesystem 120 may include a variety of storage types or media, such asmagnetic disk drive storage, flash storage, etc. In some embodiments,the techniques described herein are employed in a transceiver andinstead of being written to or read from storage, the data istransmitted and received over a channel (e.g., wired or wireless). Inthis case, the errors in the received codeword may be introduced duringtransmission of the codeword.

When the stored data is requested or otherwise desired (e.g., by anapplication or a user), the detector 130 receives the data from thestorage system 120. The received data may include some noise or errors.The detector 130 performs detection on the received data and outputsdecision and/or reliability information corresponding to one or morebits in a codeword. For example, a soft-output detector outputsreliability information and a decision for each detected bit. On theother hand, a hard output detector outputs a decision on each bitwithout providing corresponding reliability information. As an example,a hard output detector may output a decision that a particular bit is a“1” or a “0” without indicating how certain the detector is in thatdecision. In contrast, a soft output detector outputs a decision andreliability information associated with the decision. In general, areliability value indicates how certain the detector is in a givendecision. In one example, a soft output detector outputs alog-likelihood ratio (LLR) where the sign indicates the decision (e.g.,a positive value corresponds to a “1” decision and a negative valuecorresponds to a “0” decision) and the magnitude indicates how sure thedetector is in that decision (e.g., a large magnitude indicates a highreliability or certainty).

The decision and/or reliability information is passed to the decoder 140which performs decoding using the decision and/or reliabilityinformation. A soft input decoder utilizes both the decision and thereliability information to decode the codeword. A hard decoder utilizesonly the decision values in the decoder to decode the codeword. Afterdecoding, the decoded bits generated by the decoder 140 are passed tothe appropriate entity (e.g., the user or application which requestedit). With proper encoding and decoding, the information bits match thedecoded bits.

The decoder 140 may implement a number of decoding schemes (e.g.,decoding algorithms implemented using application-specific integratedcircuit (ASIC), a field-programmable gate array (FPGA), and/or a generalpurpose processor (e.g., an Advanced RISC Machine (ARM) core)) dependingon the type of the codeword and whether or not reliability informationcorresponding to each bit is available.

In an example embodiment, the decoder 140 implements multiple Chasedecoding procedures. Each implemented procedure represents a softdecoder. The soft decoders can be connected in series, as furtherillustrated in FIG. 3, or in parallel, as further illustrated in FIG. 4.U.S. patent application Ser. No. 15/460,155, filed Mar. 15, 2017,entitled “Soft Decoder for Generalized Product Codes,” U.S. patentapplication Ser. No. 15/158,416, entitled “Performance Optimization InSoft Decoding For Turbo Product Codes,” filed May 18, 2016, and U.S.patent application Ser. No. 15/431,554, filed Feb. 13, 2017, entitled“Soft Decoder Parameter Optimization For Product codes,” all of whichare commonly assigned and expressly incorporated by reference herein intheir entirety, describe examples of Chase decoding procedures.

Generally in Chase decoding, the least reliable bits (e.g., according tothe LLRs of the bits) are flipped and hard decoding is performedmultiple times. The outputs of successful hard decoding procedures aresorted according to the Euclidean distance to the received codeword, andthe closest codeword is selected as a candidate decoded codeword. Thisis usually followed by an additional procedure (e.g., miscorrectionavoidance thresholding (MAT)) to determine whether the selectedcandidate codeword (e.g., output of the Chase decoder) is the correctcodeword or if it is a miscorrected codeword. In one example, when amiscorrection is declared, no changes are made to the received codewordin that iteration of Chase decoding to avoid adding new errors in thecodeword.

In Chase (L) decoding, anytime bits are to be flipped in an attempt tocorrect errors, only “L” bits are selected and flipped (e.g., the “L”bits that have the smallest LLRs). “L” represents a decoding parameter.Hence, rather than flipping a large number of bits, a smaller number “L”can be flipped. The possible number of bit flips is accordingly reducedto “2^(L)−1.” By doing so, the decoding latency is reduced relative toChase decoding that does not limit the bit flipping according to the “L”parameter.

In Chase (L, S) decoding, anytime bits are to be flipped in an attemptto correct errors, only “L” bits are flipped. Further, when flipping “L”bits, only combinations of “S” bits can be flipped. “S” represents asecond decoding parameter. Hence, the number of possible flips isfurther reduce to (_(S) ^(L)) (e.g., combination of “S” bits from a setof “L” bits). By doing so, the decoding latency is further reducedrelative to Chase (L) decoding.

FIG. 2A and FIG. 2B are simplified schematic diagrams illustrating a GPCcodeword, in accordance with certain embodiments of the presentdisclosure. As an example, a GPC code 200 is a product code in whichinformation bits are grouped in blocks, the blocks of information bitsand one or more XOR parity blocks is arranged in a rectangular matrix ofdata blocks. In the example of FIG. 2A, the data blocks of informationbits are numbered D1-D9, and each block Dk contains “i” bits, where “i”is a positive integer. Each row of data is permuted and the codewordparity is constructed on the permuted data, which is shown as Row Parityin FIG. 2A. In addition, the parities on the parity (POP) areconstructed by combining row parities column-wise. The arrangement isconfigured to remove miscorrections because the same codeword will notbe formed for different rows with changing data locations withpermutations. All the data blocks are protected twice, however the rowparity is protected once. The parity on parity (POP) will add anotherlevel of protection to remove errors in parities.

In FIG. 2B, a specific example is shown to explain the construction of aGPC code 250. However, the construction described here can be used forany class of product codes. For example, in other embodiments, theproduct code construction can be extended to higher dimensions. In anembodiment, data blocks can be protected three times in athree-dimensional generalized product code.

In FIG. 2B, the number of data bits in a block, “i,” is taken as aninteger, for example, from eight to sixteen, but it can be any chosenvalue depending upon desired data length and code rate. Let Ncw be thenumber of row codewords, which is equal to five in FIG. 2B, i.e., thereare five codewords designated as CW1-CW5. The block designated as “XOR”or “XOR parity” is constructed by taking XOR (exclusive OR) of all datablocks of length “i,” and the parities of the first (Ncw-1) rowcodewords. In some embodiments, multiple XOR blocks can be formed, witheach XOR block constructed based on a subset of all data blocks ofinformation bits. The length of the “XOR parity” block is also equal to“i.” All row parities are further encoded by another constituent codewhich is called parity on parity or POP. In this code construction, thedecoding criterion is such that the data is decoded successfully if allNcw codewords are decodable and XOR parity check is satisfied. Thisdecoding criterion helps in avoiding miscorrections. In thisconstruction XOR is used to correct stuck patterns.

In this example, it can be seen that every pair of constituent codewordsshare a common block of data bits with each other. In other words, thesame block of data is contained in two codewords. For instance, datablock D1 is in both CW1 and CW2, and therefore, CW1 and CW2 share datablock D1. Similarly, CW1 and CW3 share data block D2, CW1 and CW4 sharedata block D3, and CW1 and CW4 share data block D4. Further, CW2 and CW3share data block D5, CW3 and CW4 share data block D8, and CW4 and CW5share the XOR data block, etc.

FIG. 3 illustrates an example configuration of a decoder 300 thatimplements multiple Chase decoding procedures, such as the decoder 140of FIG. 1, in accordance with certain embodiments of the presentdisclosure. FIG. 3 illustrates three Chase decoding procedurescorresponding to three possible stages for decoding GPC codewords.However, a different number of decoding procedures is possible, whetherthese procedures are Chase decoding procedures, another type of decodingprocedure, or a combination of different types of decoding procedures.

Generally, the Chase decoding procedures are connected in series. In anembodiment, the series connection cascades the Chase decoding procedureswhere a GPC codeword is input to a particular Chase decoding procedure.On one hand, if the decoding is successful, a decoded codeword is outputfrom the Chase decoding procedure. This output and the GPC codeword neednot be used as inputs to any of the remaining Chase decoding procedures.On the other hand, if the decoding fails, the GPC codeword becomes inputto the next Chase decoding procedure in the series. For instance, theGPC codeword is an output from the particular, failed Chase decodingprocedure and is input to the next Chase decoding procedure.

In the illustrative example of FIG. 3, a stage one faster soft decoder310 (e.g., one that implements a first Chase decoding procedure) is thefirst decoder in the series. A stage two fast soft decoder 320 (e.g.,one that implements a second Chase decoding procedure) is the seconddecoder in the series and is connected to the stage one faster softdecoder 310. A stage three slow soft decoder 330 (e.g., one thatimplements a third Chase decoding procedure) is the last decoder in theseries and is connected to the stage two fast soft decoder 320. Thethree soft decoders 310-330 form the decoder 300. Each of the threedecoders 310-330 implements a Chase decoding procedure that uses a setof decoding parameters, such as “L” and “S,” that are common across thethree decoders 310-330. The values of the parameters are optimized toachieve a desired performance (e.g., latency or BER) at the cost ofanother type of performance (e.g., BER or latency). Generally, thelarger number of bits that can be flipped, the larger the latency is andthe smaller the BER is. For instance, the “L” and “S” parameters limitthe number of combinations of possible bit flips. The smaller the numberof possible bit flips, the faster the Chase decoding procedure becomes,but the worse the BER is.

The overall latency of the system can be expressed as: overalllatency=latency of first stage coder+Σ_(i=2) ^(N)BER_(i-1)×(latency of“i^(th)” stage decoder), where “i” is an integer and “N” is the numberof stages (e.g., “N” is three in the example of FIG. 3). Because the BERat each stage is reduced relative to the previous stage, the overalllatency of the system is reduced relative to existing decoding systems.

In addition to the “L” and “S” parameters, other decoding parametersexist and can be used to optimized for performance, such as for latencyor BER. For example, the decoding parameters may further includemiscorrection avoidance thresholds (MAT) parameters, maximum iterationfor soft decoding global loop and maximum number of iterations. Itshould be noted that the values for “L,” “S,” and MAT parameters canalso change according to iteration numbers. In general, the differentdecoding parameters are optimized for latency (e.g., to achieve adesired decoding latency) or BER (e.g., such that there is no errorfloor until the desired code failure rate (CFR)). There is a tradeoff inlatency and error floor optimization. Typically, shorter latencyoptimized parameters have worse error floor. U.S. patent applicationSer. No. 15/431,554, filed Feb. 13, 2017, entitled “Soft DecoderParameter Optimization For Product codes,” which is commonly assignedand expressly incorporated by reference herein in its entirety,describes different techniques for setting the values of the decodingparameters to achieve a desired performance.

An input codeword 302, such as a GPC codeword, is input to the stage onefaster soft decoder 310. If the decoding using this first procedure issuccessful, an output codeword 312 is output from the stage one fastersoft decoder 310. Otherwise, the input codeword 302 is input to thestage two fast soft decoder 320. Here also, if the decoding using thissecond procedure is successful, an output codeword 322 is output fromthe stage two fast soft decoder 320. Otherwise, the input codeword 302is input to the stage three slow soft decoder 330. Assuming decodingsuccess, an output codeword 332 is output from the stage 3 slow softdecoder 330. Of course, if the decoding using this third procedurefailed, a next decoding procedure is used (if one exists) or a decodingfailure is declared.

In one particular embodiment, the soft decoder 310 is a Chase (8, 6)decoder. The average latency for this decoder 310 is around sixtymicroseconds, with an error floor pushed to 1 e⁻² CFR. In comparison,the soft decoder 320 is a Chase (6, 4) decoder. The average latency forthis decoder 320 is around one hundred and twenty-five microseconds,with an error floor pushed to 1 e⁻⁵ CFR. The soft decoder 330 is a Chase(10, 4) decoder. The average latency for this decoder 330 is around sixhundred microseconds, with an error floor pushed to 1 e⁻¹¹ CFR. In thisparticular embodiment, the three stage architecture has an overalllatency of 60+1 e⁻²×125+1 e⁻⁵×600=61.3 seconds. Relative to the slowestyet best BER decoder (e.g., the third stage soft decode 330 with a sixhundred microsecond latency and 1 e⁻¹¹ CFR), the three stagearchitecture can make the average latency around ten times faster (e.g.,61.3 microseconds compared to six hundred microseconds) while achievinga similar BER.

FIG. 4 illustrates another example configuration of a decoder 400 thatimplements multiple Chase decoding procedures, such as the decoder 140of FIG. 1, in accordance with certain embodiments of the presentdisclosure. Here and similarly to FIG. 3, three Chase decodingprocedures are used. However, a different number of decoding proceduresis also possible. Unlike the configuration of FIG. 3, the three Chasedecoding procedures are provided in parallel.

In an embodiment, a GPC codeword is decoded with only one of theavailable Chase decoding procedures. More specifically, a selection ismade for a particular Chase decoding procedure, where the selectiondepends on a number of factors that relate to noise and/or error. Theselected Chase decoding procedure is then used for the decoding. Theremaining Chase decoding procedures are not used for the decoding. In anexample, the factors include a BER estimate at the time of the decodingand a mapping of the Chase decoding procedures to BER ranges. Forinstance, if the BER estimate falls within a BER range that correspondsto a particular Chase decoding procedure, that procedure is selected forthe decoding.

In the particular embodiment of FIG. 4, the decoder 400 includes threesoft decoders that are provided in parallel: a stage one faster softdecoder 410, a stage two fast soft decoder 420, and a stage three slowdecoder 440. Each of these decoders implements a Chase decodingprocedure. The different Chase decoding procedures share a common set ofdecoding parameters. However, the values of these parameters varybetween the different Chase decoding procedures and are optimized for adesired performance (e.g., latency or BER). The three soft decoders 410,420, and 430 of FIG. 4 can have the same parameters and the associatedvalues as the three soft decoders 310, 320, and 330, respectively, ofFIG. 3.

In addition, the decoder 400 includes a BER estimation and stageselection module 440. This module 400 can be implemented as hardware, oras software or firmware hosted on hardware. The module 440 is configuredto select one of the three soft decoders 410, 420, and 430 given somefactors about noise and/or error. For instance, if some information onBER is available at the time of decoding, the module 440 uses thisinformation to select a particular soft decoder.

In a particular example, to select a soft decoder (or, equivalently, aChase decoding procedure), the module 440 uses BER estimate and amapping of BER ranges to the available soft decoders 410, 420, 430. Morespecifically, each of the soft decoders 410, 420, 430 operates within arange of BER. For instance, the stage one faster soft decoder 410'srange is one to 1 to 1 e⁻² CFR. The stage two fast soft decoder 420'srange is 1 e⁻² CFR to 1 e⁻⁵ CFR. The stage three slow soft decoder 430'srange is 1 e⁻⁵ CFR to 1 e⁻¹¹ CFR. The mapping associates each of thesoft decoders 410, 420, 430 with one of such ranges. If the BER estimatefalls in a particular range, the module 440 selects the soft decoderthat is associated with that range.

The mapping can be developed through simulation, as further illustratedin FIG. 8. Briefly, once the decoding parameters of a soft decoder areset to particular values to achieve, for example, a particular latencyperformance, the BER performance of the soft decoder is simulated. Giventhe BER performance simulation, the BER range is derived. The mapping isupdated to map this BER range to an identifier of the soft decoder.

Various techniques are also available to determine the BER estimate andshould be apparent to one skilled in the art. In one example, the BERestimate is available from memory of a flash storage device from whichGPC codewords are read. In another example, the module 440 estimates anobserved BER. To do so, the module uses a weight vector “W.” This weightvector “W” is available from memory of the system that implements thedecoder 400. The weight vector “W” is derived prior to the decoding,such as during a simulation phase. In the simulation phase, trainingcodewords are used during a simulation phase. The training codewords(represented as a matrix “TC”) are input to the decoder 400 at knownBERs (represented as a vector “B”). The weight vector “W” is thecomputed, where the product of “TC” and “W” is the BER vector “B.” Uponcompletion of the simulation phase, the weight vector “W” is stored inthe memory of the system. Thereafter and upon decoding differentcodewords (represented as a matrix “DC”), the observed BER is estimatedas the product of “DC” and “W.”

As illustrated in FIG. 4, an input codeword 402, such as a GPC codeword,is input to the decoder 400. The BER estimation and stage selectionmodule 440 selects one of the three soft decoders 410, 420, or 430 todecode this input codeword 412. Similarly, if the stage two fast softdecoder 420 is selected instead, this second decoder is used for thedecoding and outputs an output codeword 422. Likewise, if the stagethree slow soft decoder 430 is selected instead of both first twodecoders, this third decoder is used for the decoding and outputs anoutput codeword 432. Here, the latency performance of the decoder 400 issimilar to the decoder 300 of FIG. 3 (about 61.3 microseconds) becauseonly the soft decoders 410, 420, and 430 are intelligently selected forthe decoding given the available information about BER.

Turning to FIGS. 5-7, the figures illustrate example flows for decodinga codeword. A system, such as an ECC system or a decoding system withinthe ECC system, may be configured to perform the illustrative flows.Instructions for performing the operations of the illustrative flows canbe stored as computer-readable instructions on a non-transitorycomputer-readable medium of the system. As stored, the instructionsrepresent programmable modules that include code or data executable by aprocessor of the system. The execution of such instructions configuresthe system to perform the specific operations shown in the figures anddescribed herein. While the operations are illustrated in a particularorder, it should be understood that no particular order is necessary andthat one or more operations may be omitted, skipped, and/or reordered.Further, some operations are similar. In the interest of clarity ofexplanation, description of the similar operations is not repeated.

FIG. 5 illustrates an example flow for decoding a codeword based on atleast one of a plurality of decoders available on the system, inaccordance with certain embodiments of the present disclosure. Each ofthe decoders implements a decoding procedure, such as a Chase decodingprocedure. In turn, the different decoding procedures implement the samedecoding algorithm, but use different values for decoding parameters ofthe decoding algorithm. The values are set for each decoder as atradeoff between latency and BER.

The example flow starts at operation 502, where the system provides aplurality of Chase decoding procedures. For example, the system includesa combination of hardware, software, and firmware to host a plurality ofsoft decoders. Each decoder implements a Chase decoding procedure. Thedecoding parameters, including “L,” “S” and any other applicabledecoding parameters, are set to achieve a particular latency performanceand a particular BER performance. The different decoders can beconnected in series, as illustrated in FIG. 3, or can be provided inparallel, as illustrated in FIG. 4.

At operation 504, the system access a GPC codeword. For example, thesystem includes a storage device. The GPC codeword is read from thestorage device. If multiple GPC codewords are also stored, thesecodewords can be similarly read.

At operation 506, the system identifies at least one of the plurality ofChase decoding procedures for decoding the GPC codeword (and, similarly,other read GPC codewords from the storage device). The identificationdepends on the configuration of the soft decoders. On one hand, if aseries configuration is used, the system identifies the first softdecoder in the series and inputs the GPC codeword to that first softdecoder. If the decoding fails at the first soft decoder, the systemthen identifies the next soft decoder in the series and inputs the GPCcodeword thereto, and so on a so forth. On the other hand, if a parallelconfiguration is used, the system selects one of the soft decoders basedon a BER estimate and a mapping of BER ranges to the soft decoders. TheGPC codeword is then input to only the selected soft decoder.

At operation 508, the system decodes the GPC codeword (and, similarly,the other read GPC codewords) by using the identified Chase decodingprocedure(s). Here again, the decoding depends on the configuration ofthe soft decoders. In the case of the series configuration, the GPCcodeword is decoded as an output from one of the soft decoders. If noneof the soft decoders successfully decodes the GPC codeword, the systemcan declare a decoding failure. In the case of the parallelconfiguration, the GPC codeword is decoded as an output from theselected soft decoder only. If that soft decoder fails to decode the GPCcodeword, the system can declare a decoding failure. Alternatively, thesystem can attempt to further decoder the GPC codeword by selecting andusing a soft decoder that has a better BER performance. However, alatency penalty can be incurred for performing the additional decoding.Hence, in latency-sensitive product applications, the additionaldecoding can be skipped.

FIG. 6 illustrates an example flow for decoding a codeword based on aseries of decoders, in accordance with certain embodiments of thepresent disclosure. In particular, the plurality of soft decoders areconnected in series, as illustrated in FIG. 3.

The example flow starts at operation 602, where the system access a GPCcodeword. This operation is similar to operation 502 of FIG. 5.

At operation 604, the system inputs the GPC codeword to a next stageChase decoding procedure. For example, at the start of the decoding(e.g., the GPC codeword has not been decoded or provided as input to anyof the soft decoders), the GPC codeword is input to the first softdecoder in the series. During the decoding, if a particular soft decoderfails to decode the GPC codeword, the GPC codeword becomes input to thenext soft decoder in the series (e.g., to the second soft decoder if thefirst one failed to decode the GPC codeword).

At operation 606, the system decodes the GPC codeword using the nextstage Chase decoding procedure. For example, the GPC codeword is decodedaccording to the decoding parameters available at that stage. Thedecoding parameters result in particular latency and BER performances.

At operation 608, the system determines whether a decoding failureoccurred or not. This determination is an output of the soft decoder. Ifno failure occurred, operation 610 is performed where the system outputsthe decoded codeword. In particular, the decoded codeword is an outputof the soft decoder. If a failure occurred, operation 612 is performedwhere the system determines if there are any remaining Chase decodingprocedures in the series. If so, the system loops back to operation 604,where the GPC codeword becomes input to the next soft decoder in theseries. Otherwise, no remaining Chase decoding procedures exist andoperation 614 is performed where the system declares a decoding failure.

FIG. 7 illustrates an example flow for decoding a codeword based onparallel decoders, in accordance with certain embodiments of the presentdisclosure. In particular, the plurality of soft decoders are providedin a parallel configuration, as illustrated in FIG. 4.

The example flow starts at operation 702, where the system access a GPCcodeword. This operation is similar to operation 502 of FIG. 5.

At operation 704, the system determines a BER estimate. For example,information about the BER estimate is available from memory of thesystem. In another example, the system estimates the BER based on aweight vector “W” and the GPC codeword. The weight vector “W” can beavailable from the memory. The BER is estimated as a product of theweight vector “W” and the GPC codeword (or a plurality of GPC codewordsthat are to be decoded from the storage device).

At operation 706, the system selects one of the available Chase decodingprocedures based on a mapping and the BER estimate. For example, themapping associated BER ranges with the soft decoders and is availablefrom the memory. The system compares the BER estimate to the BER rangesand selects the soft decoder associated with the BER range in which theBER estimate falls.

At operation 708, the system decodes the GPC codeword by using theselected Chase decoding procedure. For example, the GPC codeword isinput to the selected soft decoder. A decoded codeword is an output ofthe selected soft decoder, unless the decoding fails. If the decodingfails, the system can declare a decoding failure.

FIG. 8 illustrates an example flow for configuring the system describedin connection with FIGS. 5-7 to achieve a desired decoding performance,such as a desired overall latency. The configuring generally includessetting values for decoding parameters and occurs prior to deploying orusing the system for decoding codewords. For example, the system (or adesign thereof) is configured in a development phase during whichvarious simulations and design adjustments are possible.

The example flow starts at operation 802, where the number of Chasedecoding procedures to implement on the system is identified. Each ofthe procedures can correspond to one stage of decoding. In general, thelarger the number, the more complex the system becomes and the more SoCmay be needed. In addition, a determination is made as to whether aseries or parallel configuration should be used. This determination candepend on whether the BER estimate will be available to the system ornot.

At operation 804, a first decoding latency is allocated from an overalldecoding latency of the system to a Chase decoding procedure. Forexample, for a faster stage one soft decoder, a sixty microsecondlatency may be allocated from an overall sixty-two second microsecondlatency. Generally, the overall decoding latency is driven by theproduct application that the system needs to support.

At operation 806, decoding latencies of the Chase decoding procedure issimulated by varying the values of the decoding parameters of the Chasedecoding procedure. For example, different values for the “L” and “S”parameters can be used to simulate the resulting decoding latency.

At operation 808, values are selected based on the simulation. Forexample, the particular values that resulted in a decoding latency equalto or smaller than the allocated decoding frequency are selected.

At operation 810, the BER performance of the Chase decoding procedure issimulated based on the selected values. For example, different trainingGPC codewords are decoded with the Chase decoding procedure having theselected values set for the decoding parameters. The BER performance ismeasured from this decoding. This performance can include a range ofBERs that the Chase decoding procedure is expected to support.

At operation 812, a mapping is updated based on the simulated BERperformance. For example, the mapping identifies the Chase decodingprocedure (and, optionally, the values of the decoding parameters), andassociates the Chase decoding procedure with the BER range that shouldbe supported.

At operation 814, an adjusted latency for a next Chase decodingprocedure is computed based on an allocated decoding latency to thisnext Chase decoding procedure and the simulated BER. The next Chasedecoding procedure corresponds to the next soft decoder in the series inthe parallel configuration. Similarly to operation 804, a decodinglatency can be allocated to this decoder from the overall decodinglatency. In particular, a remaining decoding latency is computed. Forexample, the remaining decoding latency is equal to the overall decodinglatency minus the allocated decoding latency of the previous stage softdecoder. However, the allocated latency should be adjusted to reflectthe fact that this decoder is only used if the decoding fails from theprevious decoder (in the case of a series configuration) or is not usedgiven some BER estimate (in the case of a parallel configuration). In anexample, the adjusted latency is equal to the allocated decoding latencydivided by the simulated average BER of the previous stage soft decoder.To illustrate, if the overall decoding latency is sixty-twomicroseconds, and the sixty microseconds were allocated to the firststage soft decoder with a simulated average BER of 1 e⁻², a twomicrosecond latency remains. In this example, one microsecond of thisremaining decoding latency is allocated to the second stage decoder.Accordingly, the adjusted latency should be equal to 1 e⁻², the adjusteddecoding latency is 1/1 e⁻²=100 microseconds. This adjusted decodinglatency is then used to set the values of the decoding parameters of thenext decoding Chase procedure. Accordingly, the operations 804-814 arerepeated for the next stage soft decoder(s), with a modification tooperation 804 where the modification allocates a decoding latency fromthe remaining decoding latency and adjusts the allocation given BER of aprevious stage soft decoder.

FIG. 9 describes one potential implementation of a system, which may beused according to one embodiment, such as the system 100 of FIG. 1. FIG.9 is merely illustrative of an embodiment of the present disclosure anddoes not limit the scope of the disclosure as recited in the claims. Inone embodiment, the system is a computer system 900 that typicallyincludes a monitor 910, a computer 920, user output devices 930, userinput devices 940, communications interface 950, and the like. Thesystem 100 of FIG. 1 implements some or all of the components of thecomputer system 900.

As shown in FIG. 9, the computer 920 may include a processor(s) 960 thatcommunicates with a number of peripheral devices via a bus subsystem990. These peripheral devices may include the user output devices 930,the user input devices 940, the communications interface 950, and astorage subsystem, such as random access memory (RAM) 970 and disk drive980.

The user input devices 930 include all possible types of devices andmechanisms for inputting information to the computer system 920. Thesemay include a keyboard, a keypad, a touch screen incorporated into thedisplay, audio input devices such as voice recognition systems,microphones, and other types of input devices. In various embodiments,the user input devices 930 are typically embodied as a computer mouse, atrackball, a track pad, a joystick, wireless remote, drawing tablet,voice command system, eye tracking system, and the like. The user inputdevices 930 typically allow a user to select objects, icons, text andthe like that appear on the monitor 910 via a command such as a click ofa button or the like.

The user output devices 940 include all possible types of devices andmechanisms for outputting information from the computer 920. These mayinclude a display (e.g., the monitor 910), non-visual displays such asaudio output devices, etc.

The communications interface 950 provides an interface to othercommunication networks and devices. The communications interface 950 mayserve as an interface for receiving data from and transmitting data toother systems. Embodiments of the communications interface 950 typicallyinclude an Ethernet card, a modem (telephone, satellite, cable, ISDN),(asynchronous) digital subscriber line (DSL) unit, FireWire interface,USB interface, and the like. For example, the communications interface950 may be coupled to a computer network, to a FireWire bus, or thelike. In other embodiments, the communications interfaces 950 may bephysically integrated on the motherboard of the computer 920, and may bea software program, such as soft DSL, or the like.

In various embodiments, the computer system 900 may also includesoftware that enables communications over a network such as the HTTP,TCP/IP, RTP/RTSP protocols, and the like. In alternative embodiments ofthe present disclosure, other communications software and transferprotocols may also be used, for example IPX, UDP or the like. In someembodiments, the computer 920 includes one or more Xeon microprocessorsfrom Intel as the processor(s) 960. Further, one embodiment, thecomputer 920 includes a UNIX-based operating system.

The RAM 970 and the disk drive 980 are examples of tangible mediaconfigured to store data such as embodiments of the present disclosure,including executable computer code, human readable code, or the like.Other types of tangible media include floppy disks, removable harddisks, optical storage media such as CD-ROMS, DVDs and bar codes,semiconductor memories such as flash memories, non-transitoryread-only-memories (ROMS), battery-backed volatile memories, networkedstorage devices, and the like. The RAM 970 and the disk drive 980 may beconfigured to store the basic programming and data constructs thatprovide the functionality of the present disclosure.

Software code modules and instructions that provide the functionality ofthe present disclosure may be stored in the RAM 970 and the disk drive980. These software modules may be executed by the processor(s) 960. TheRAM 970 and the disk drive 980 may also provide a repository for storingdata used in accordance with the present disclosure.

The RAM 970 and the disk drive 980 may include a number of memoriesincluding a main random access memory (RAM) for storage of instructionsand data during program execution and a read only memory (ROM) in whichfixed non-transitory instructions are stored. The RAM 970 and the diskdrive 980 may include a file storage subsystem providing persistent(non-volatile) storage for program and data files. The RAM 970 and thedisk drive 980 may also include removable storage systems, such asremovable flash memory.

The bus subsystem 990 provides a mechanism for letting the variouscomponents and subsystems of the computer 920 communicate with eachother as intended. Although the bus subsystem 990 is shown schematicallyas a single bus, alternative embodiments of the bus subsystem mayutilize multiple busses.

FIG. 9 is representative of a computer system capable of embodying thepresent disclosure. It will be readily apparent to one of ordinary skillin the art that many other hardware and software configurations aresuitable for use with the present disclosure. For example, the computermay be a desktop, portable, rack-mounted, or tablet configuration.Additionally, the computer may be a series of networked computers.Further, the use of other microprocessors are contemplated, such asPentium™ or Itanium™ microprocessors; Opteron™ or AthlonXP™microprocessors from Advanced Micro Devices, Inc; and the like. Further,other types of operating systems are contemplated, such as Windows®,WindowsXP®, WindowsNT®, or the like from Microsoft Corporation, Solarisfrom Sun Microsystems, LINUX, UNIX, and the like. In still otherembodiments, the techniques described above may be implemented upon achip or an auxiliary processing board.

Various embodiments of the present disclosure can be implemented in theform of logic in software or hardware or a combination of both. Thelogic may be stored in a computer readable or machine-readablenon-transitory storage medium as a set of instructions adapted to directa processor of a computer system to perform a set of steps disclosed inembodiments of the present disclosure. The logic may form part of acomputer program product adapted to direct an information-processingdevice to perform a set of steps disclosed in embodiments of the presentdisclosure. Based on the disclosure and teachings provided herein, aperson of ordinary skill in the art will appreciate other ways and/ormethods to implement the present disclosure.

The data structures and code described herein may be partially or fullystored on a computer-readable storage medium and/or a hardware moduleand/or hardware apparatus. A computer-readable storage medium includes,but is not limited to, volatile memory, non-volatile memory, magneticand optical storage devices such as disk drives, magnetic tape, CDs(compact discs), DVDs (digital versatile discs or digital video discs),or other media, now known or later developed, that are capable ofstoring code and/or data. Hardware modules or apparatuses describedherein include, but are not limited to, application-specific integratedcircuits (ASICs), field-programmable gate arrays (FPGAs), dedicated orshared processors, and/or other hardware modules or apparatuses nowknown or later developed.

The methods and processes described herein may be partially or fullyembodied as code and/or data stored in a computer-readable storagemedium or device, so that when a computer system reads and executes thecode and/or data, the computer system performs the associated methodsand processes. The methods and processes may also be partially or fullyembodied in hardware modules or apparatuses, so that when the hardwaremodules or apparatuses are activated, they perform the associatedmethods and processes. The methods and processes disclosed herein may beembodied using a combination of code, data, and hardware modules orapparatuses.

Although the foregoing embodiments have been described in some detailfor purposes of clarity of understanding, the disclosure is not limitedto the details provided. There are many alternative ways of implementingthe disclosure. The disclosed embodiments are illustrative and notrestrictive.

What is claimed is:
 1. A system for codeword decoding, comprising: aprocessor; a memory communicatively coupled with the processor andstoring instructions that, upon execution by the processor, cause thesystem to at least: access a generalized product code (GPC) codeword;and decode the GPC codeword by using at least one of a plurality ofChase decoding procedures available on the system, wherein: theplurality of Chase decoding procedures comprise a first Chase decodingprocedure and a second Chase decoding procedure that are configuredbased on a set of decoding parameters, the set of decoding parameterscomprising a first parameter that limits a first total number of bitsavailable for flipping across multiple flips, the set of decodingparameters further comprising a second parameter that limits a secondtotal number of bits available for flipping in a single flip, the firstChase decoding procedure is configured according to first values for theset of decoding parameters, the first values specified for at least thefirst total number and the second total number of the second decodingChase decoding procedure, the second Chase decoding procedure isconfigured according to second values for the set of decodingparameters, the second values specified for at least the first totalnumber and the second total number of the second decoding Chase decodingProcedure, at least one of the first total number or the second totalnumber is defined differently for the first Chase decoding procedure andthe second Chase decoding procedure based on the second values beingdifferent from the first values, and the first Chase decoding procedurehas a smaller latency and a higher bit error rate (BER) relative to thesecond Chase decoding procedure based on the first values and the secondvalues for the set of decoding parameters.
 2. The system of claim 1, thefirst total number is “L” bits of the GPC codeword available forflipping across the multiple flip by a Chase (L,S) decoding procedure.3. The system of claim 2, wherein the second total number is “S” bits ofthe GPC codeword available for flipping in the single flip by the Chase(L,S) decoding procedure.
 4. The system of claim 3, wherein a firstcombination of the first parameter and the second parameter for thefirst Chase decoding procedure has a smaller number of possible bitflips than a second a second combination of the first parameter and thesecond parameter for the second Chase decoding procedure.
 5. The systemof claim 1, wherein the first Chase decoding procedure and the secondChase decoding procedure are provided in series.
 6. The system of claim5, wherein the GPC codeword is input to the first Chase decodingprocedure, and wherein: if the first Chase decoding procedure fails todecode the GPC codeword, the GPC codeword is input to the second Chasedecoding procedure and is decoded according to the second Chase decodingprocedure, and if the first Chase procedure decoding succeeds indecoding the GPC codeword, the GPC codeword is decoded according to thefirst Chase decoding procedure and is not input to the second Chasedecoding procedure.
 7. The system of claim 5, wherein the first valuesfor the set of decoding parameters are set for the first Chase decodingprocedure based on: an allocation of a first latency from an overalllatency of the system to the first Chase decoding procedure; asimulation of latencies of the first Chase decoding procedure, whereinthe simulation varies the first values; and a selection of particularvalues from the varied first values based on the simulation of thelatencies, wherein the particular values correspond to a simulatedlatency that is equal to or smaller than the first latency.
 8. Thesystem of claim 7, wherein the second values for the set of decodingparameters are set for the second Chase decoding procedure based on: asimulation of a first BER of the first Chase decoding procedure, whereinthe first BER corresponds to the particular values set as the firstvalues of the first Chase decoding procedure; a computation of aremaining latency based on the overall latency and the first latency;and an allocation of a second latency from the remaining latency to thesecond Chase decoding procedure; and a computation of an adjustedlatency, wherein the computation of the adjusted latency uses the firstBER of the first Chase and the second latency.
 9. The system of claim 1,wherein the first Chase decoding procedure and the second Chase decodingprocedure are provided in parallel.
 10. The system of claim 9, whereinonly one of the first Chase decoding procedure or the second Chasedecoding procedure is selected for the decoding of the GPC codeword. 11.The system of claim 10, wherein the instructions further cause thesystem to at least select the first Chase decoding procedure or thesecond Chase decoding procedure based on a BER estimate and a mapping ofBER ranges to a plurality of Chase decoding procedures available on thesystem, wherein the plurality of Chase decoding procedures comprises thefirst Chase decoding procedure and the second Chase decoding procedure.12. The system of claim 11, wherein the first values for the set ofdecoding parameters are set for the first Chase decoding procedure basedon: an allocation of a first latency from an overall latency of thesystem to the first Chase decoding procedure; a simulation of latenciesof the first Chase decoding procedure, wherein the simulation varies thefirst values; a selection of particular values from the varied firstvalues based on the simulation of the latencies, wherein the particularvalues correspond to a simulated latency that is equal to or smallerthan the first latency; a simulation of a first BER of the first Chasedecoding procedure, wherein the first BER corresponds to the particularvalues set as the first values of the first Chase decoding procedure;and an update to the mapping of BER ranges based on a simulation of thefirst BER.
 13. A method for codeword decoding, the method comprising:accessing, by a system, a generalized product code (GPC) codeword; anddecoding, by the system, the GPC codeword by using at least one of aplurality of Chase decoding procedures available on the system, wherein:the plurality of Chase decoding procedures comprise a first Chasedecoding procedure and a second Chase decoding procedure that areconfigured based on a set of decoding parameters, the set of decodingparameters comprising a first parameter that limits a first total numberof bits available for flipping across multiple flips, the set ofdecoding parameters further comprising a second parameter that limits asecond total number of bits available for flipping in a single flip, thefirst Chase decoding procedure is configured according to first valuesfor the set of decoding parameters, the first values specified for atleast the first total number and the second total number of the seconddecoding Chase decoding procedure, the second Chase decoding procedureis configured according to second values for the set of decodingparameters, the second values specified for at least the first totalnumber and the second total number of the second decoding Chase decodingprocedure, at least one of the first total number or the second totalnumber is defined differently for the first Chase decoding procedure andthe second Chase decoding procedure based on the second values beingdifferent from the first values, and the first Chase decoding procedurehas a smaller latency and a higher bit error rate (BER) relative to thesecond Chase decoding procedure based on the first values and the secondvalues for the set of decoding parameters.
 14. The method of claim 13,wherein the first Chase decoding procedure and the second Chase decodingprocedure are available on the system in series, wherein the GPCcodeword is input to the first Chase decoding procedure, and wherein: ifthe first Chase decoding procedure fails to decode the GPC codeword, theGPC codeword is input to the second Chase decoding procedure and isdecoded according to the second Chase decoding procedure, and if thefirst Chase procedure decoding succeeds in decoding the GPC codeword,the GPC codeword is decoded according to the first Chase decodingprocedure and is not input to the second Chase decoding procedure. 15.The method of claim 13, wherein the first Chase decoding procedure andthe second Chase decoding procedure are available on the system inparallel, and wherein only one of the first Chase decoding procedure orthe second Chase decoding procedure is selected for the decoding of theGPC codeword.
 16. The method of claim 15, wherein the operations furthercomprise selecting, by the system, the first Chase decoding procedure orthe second Chase decoding procedure based on a BER estimate and amapping of BER ranges to the plurality of Chase decoding proceduresavailable on the system.
 17. A non-transitory computer-readable storagemedium storing instructions that, upon execution by a processor of asystem, configure the system to perform operations comprising: accessinga generalized product code (GPC) codeword; and decoding the GPC codewordby using at least one of a plurality of Chase decoding proceduresavailable on the system, wherein: the plurality of Chase decodingprocedures comprise a first Chase decoding procedure and a second Chasedecoding procedure that are configured based on a set of decodingparameters, the set of decoding parameters comprising a first parameterthat limits a first total number of bits available for flipping acrossmultiple flips, the set of decoding parameters further comprising asecond parameter that limits a second total number of bits available forflipping in a single flip, the first Chase decoding procedure isconfigured according to first values for the set of decoding parameters,the first values specified for at least the first total number and thesecond total number of the second decoding Chase decoding procedure, thesecond Chase decoding procedure is configured according to second valuesfor the set of decoding parameters, the second values specified for atleast the first total number and the second total number of the seconddecoding Chase decoding procedure, at least one of the first totalnumber or the second total number is defined differently for the firstChase decoding procedure and the second Chase decoding procedure basedon the second values being different from the first values, and thefirst Chase decoding procedure has a smaller latency and a higher biterror rate (BER) relative to the second Chase decoding procedure basedon the first values and the second values for the set of decodingparameters.
 18. The non-transitory computer-readable storage medium ofclaim 17, wherein the first Chase decoding procedure and the secondChase decoding procedure are available on the system in series, whereinthe GPC codeword is input to the first Chase decoding procedure, andwherein: if the first Chase decoding procedure fails to decode the GPCcodeword, the GPC codeword is input to the second Chase decodingprocedure and is decoded according to the second Chase decodingprocedure, and if the first Chase procedure decoding succeeds indecoding the GPC codeword, the GPC codeword is decoded according to thefirst Chase decoding procedure and is not input to the second Chasedecoding procedure.
 19. The non-transitory computer-readable storagemedium of claim 17, wherein the first Chase decoding procedure and thesecond Chase decoding procedure are available on the system in parallel,and wherein only one of the first Chase decoding procedure or the secondChase decoding procedure is selected for the decoding of the GPCcodeword.
 20. The non-transitory computer-readable storage medium ofclaim 19, wherein the instructions further configure the system to atleast select the first Chase decoding procedure or the second Chasedecoding procedure based on a BER estimate and a mapping of BER rangesto the plurality of Chase decoding procedures available on the system.